Open AccessFPGA Implementation of Area Efficient CMOS Multiplier using Fast Kogge Stone Look Ahead Logarithmic Adder
Author(s) -
L. Malathi,
Divya Bharathi,
D. Jayanthi
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.d9714.118419
Subject(s) - adder , multiplier (economics) , arithmetic , computer science , carry save adder , parallel computing , serial binary adder , field programmable gate array , pipeline (software) , binary number , cmos , computer hardware , mathematics , electronic engineering , engineering , economics , macroeconomics , programming language
Though Multipliers play a major role in all digital processing systems, still there is a research challenge related with area, delay, power, speed and accuracy parameters. Basically multipliers contains more number of adders (i.e.,) multiplication is done by repetitive additions. Highest care should be taken on adders. Partial Products (PP) part is middle process between multiplier, multiplicand and final addition. Next one about the methodology that Serial/parallel, Pipeline/parallel, Floating/decimal, Array, Binary/BCD, Fixed/Variable, Gate Level/Transistor Level. All the predecessors are having more controversy parameters. The forthcoming research concentrated on parallel, pipelining, decimal, binary and transistor level.