Open AccessA Low Jitter – Low Phase Noise Wideband Digital Phase Locked Loop In Nanometer Cmos Technology
Author(s) -
Nirav P. Patel,
Amisha Naik,
Priyesh P. Gandhi
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.d8615.118419
Subject(s) - jitter , phase locked loop , phase noise , dbc , wideband , cmos , pll multibit , electronic engineering , offset (computer science) , power consumption , computer science , electrical engineering , materials science , power (physics) , physics , engineering , programming language , quantum mechanics
For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents similar design for 7.5-GHz Phase locked loop in 180 nm CMOS technology. The measured phase noise of the proposed PLL with self aligned injection at 1 MHz offset is 121.14 dBc/Hz and rms jitter is 110 fs. The total dc power consumption is 13.99 mW. To support the claim process variation with design corner analysis using random variations are carried out.