A Fault Tolerant Han-Carlsonadder using Tmr Technique | Zendy

S. Rooban | Zendy; Padakanti Divya | Zendy; P. Sai Preethi | Zendy; M. Divya | Zendy

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A Fault Tolerant Han-Carlsonadder using Tmr Technique

Author(s) -

S. Rooban,

Padakanti Divya,

P. Sai Preethi,

M. Divya

Publication year - 2019

Publication title -

international journal of recent technology and engineering (ijrte)

Language(s) - English

Resource type - Journals

ISSN - 2277-3878

DOI - 10.35940/ijrte.d8227.118419

Subject(s) - voting , fault tolerance , adder , redundancy (engineering) , triple modular redundancy , computer science , majority rule , field programmable gate array , arithmetic , embedded system , mathematics , telecommunications , distributed computing , artificial intelligence , political science , latency (audio) , operating system , politics , law

A fault tolerant Han-Carlson adder is implemented using TMR technique. This paper suggests a technique of Triple Mode Redundancy (TMR) in which the vote is processedto produce a single output by a majority voting system.Synthesis and simulation are performed using Vivado(Xilinx). The circuitry is basically repeated in triplicate, as the name suggests, with a voting circuit used to transmit to the output the majority rule signals.

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