Open AccessA Fault Tolerant Han-Carlsonadder using Tmr Technique
Author(s) -
S. Rooban,
P. Divya,
P.Sai Preethi,
M. Divya
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.d8227.118419
Subject(s) - voting , fault tolerance , redundancy (engineering) , adder , computer science , triple modular redundancy , field programmable gate array , majority rule , arithmetic , embedded system , mathematics , distributed computing , telecommunications , political science , artificial intelligence , operating system , latency (audio) , politics , law
A fault tolerant Han-Carlson adder is implemented using TMR technique. This paper suggests a technique of Triple Mode Redundancy (TMR) in which the vote is processedto produce a single output by a majority voting system.Synthesis and simulation are performed using Vivado(Xilinx). The circuitry is basically repeated in triplicate, as the name suggests, with a voting circuit used to transmit to the output the majority rule signals.