Open AccessPerformance of Improved speed pipelined floating point multiplier Architecture
Author(s) -
Rr. Ghina Ayu P.T.K
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.d8055.118419
Subject(s) - multiplier (economics) , floating point , digital signal processing , adder , arithmetic , booth's multiplication algorithm , computer science , integer (computer science) , computer hardware , algorithm , digital signal processor , mathematics , parallel computing , telecommunications , latency (audio) , economics , macroeconomics , programming language
Multiplier is a hardware component which usually covers an important chip area and must be reduced to create lots of functions in which multiplier frames shape an essential structure, including digital signal processing (DSP) systems and analytical approaches. The benefit of floating point representation across a fixed point (and integer) view is that a wider range of values can be represented. Since floating point numbers are stored in sign-magnitude type, the multiplier also requires unwritten integer numbers and standardization. The multiplier with the algorithm Revised Booth and save adder is one way to speed up the multiplier. The algorithm of Revised Booth reduces the number of incomplete products to create and is regarded as the quickest algorithm of propagation.