Artificial Intelligence Algorithmic Based Fault Tolerance with OLC Codes for Parallel Fault Detection and Correction FFT Soc Design

Different errors are attacks the VLSI SoC designs these are harm to Mathematical operations and obstacles to results because of this soft core errors are trending to screen. With the increase of information communication, sources of noise (SON) and interference and parallel processing, increases the fault tolerances so designers have been striving to achieve with the require for extra competent and consistent techniques for detecting and correcting faults in parallel “transmission_(TX)” and “reception_(RX)” of data. even if some methods and advances have been projected and apply in past years but information dependability in TX and TX is at rest a trouble. In this research we recommend a more efficient mutual “error_detection” & “correction_technique” stand on the Artificial intelligent algorithmic based fault tolerance (AIABFT) with parallel Orthogonal Codes, and vertical parity. With the help of proposed method designing a parallel processing faults detection and correction FFT. This AIABFT method has been experimentally executed and replicated using Xilinx_vivadoResults of the simulation indicate that the suggested method detects 97% of the mistakes and corrections as expected in the received impaired n-bit code up to (n/2-1) bits of mistakes