Open AccessHigh Speed FIR Filter Design using Multiplier Sharing and Sub-Expression Elimination Method
Author(s) -
C. M.,
Priti Sharma,
K. Vishnu Vardhan,
S Ramya
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.d5310.118419
Subject(s) - adder , computer science , finite impulse response , filter (signal processing) , filter design , lookup table , multiplier (economics) , linear phase , digital filter , electronic engineering , digital signal processing , half band filter , low pass filter , adaptive filter , computer hardware , algorithm , root raised cosine filter , engineering , telecommunications , economics , computer vision , macroeconomics , programming language , latency (audio)
FIR filter is the basic filter used in many DSP applications because of its linear phase , stability , low cost and simple structure . Designing a high- speed and hardware efficient FIR filter is a very difficult task as the complexity increases with the filter order .In most Application the higher order filters are required but the memory usage of filter increases exponentially with the order of the filter using multipliers occupy a large chip area and need more access time. So the design and implementation of highly efficient look up table (LUT) based circuit for the implementation using DA Algorithm increases the speed. Multiplier sharing and sub-expression elimination methods are proposed to optimize the Structural adders. These methods split the structural adders into smaller adder blocks to reduce the delay. In order to reduce the complexity of structural adders round-off can be performed at the cost of sacrificing precision of the filter.