Modified Encryption Standard with High Performance through Secure Protocol

The Advanced Encryption Standard (AES) has been accepted worldwide as a desirable algorithm to encryption and decryption sensitive information. In cryptography the unencrypted information referrers to as plaintext it is encrypted into cipher-text, which will in turn be decrypted back into the usable plaintext. The encryption and decryption are based on the type of cryptography system and secret keys. The secret key is responsible for preparing the input key to be used by the cipher in each round. AES with one-stage pipeline producing minor reduction of delay but does not show any improvement in area and power consumption. To overcome the above drawbacks, the basic architecture of AES, which includes encryption and decryption can be modified with one stage pipeline architecture by using one- dimensional Substitute Box (SBOX). Advanced Microcontroller Bus Architecture (AMBA) describes level of an on-chip communication standards for elevated performance embedded microcontrollers. AMBA AHB (Advanced High Performance Bus) is intended for elevated performance and high-frequency clocks. AHB has unique characteristics such as burst transfer, split transaction and single-cycle master bus transfer. 128 bit plain text is guided by AMBA-AHB requirements and can be used to send a plain text block to the cypher per clock cycle.. Plain text of 128 bit is driven by AMBAAdvanced High-performance Bus. AMBA-AHB specifications and supports the transmission to the cipher of a plain text block per clock cycle i.e., Modified Encryption Standard will be implemented with AMBA –AHB driven by input, which provides on-chip communication, increasing security of encryption standard. Propositioning methodology, Modified Encryption Standard will be simulated and synthesized by using Xilinx ISim 14.7 FPGA.