Open AccessOn-Chip Hardware Accelerator For DSP Applications
Author(s) -
Swati Sanjay Patil*,
B. G. Nagaraja
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.c6079.098319
Subject(s) - computer science , field programmable gate array , digital signal processing , throughput , embedded system , computer hardware , hardware acceleration , chip , computer architecture , multi core processor , operating system , wireless , telecommunications
High speed computing systems developed for multimedia streaming application demand high throughput and which can be achieved by designing hardware accelerators for data processing. This article presents new hardware accelerating platform comprised of heterogeneous multi core processing elements integrated on single chip FPGA. This kind of multi core platform can boost multimedia applications through parallel processing. The proposed multi core platform has been realized on FPGA and few DSP applications are executed on the processing elements of the platform to validate its performance. The performance of the proposed hardware accelerator has been compared with existing standard computing platforms frequently used for multimedia applications. The comparison shows that the proposed on-chip multi core accelerator has enhanced the execution speed of DSP applications while providing optimum throughput.