Open AccessPerformance Evaluation of New Adder Designed for Electronic Circuits
Author(s) -
R. Gowrishankar*,
Dr.N. Sathishkumar,
Dr.B. Senthilkumar*
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.c5681.098319
Subject(s) - adder , arithmetic , computer science , carry save adder , arithmetic logic unit , serial binary adder , parallel computing , electronic circuit , computation , power consumption , power (physics) , computer hardware , mathematics , algorithm , engineering , telecommunications , electrical engineering , physics , quantum mechanics , latency (audio)
Arithmetic and Logic Unit (ALU) is the important module in any digital system utilized in the current world applications. Adder plays major role in the construction of any ALU. Multipliers can also be designed with the help of continuous addition. The efficient design of adders is very much needed for the efficient ALU design. Parallel prefix adder has been chosen in this research because of its fastest computation and efficiency. Kogge Stone, Sklansky, Ladner Fischer, Brunt Kung, Han-Carlson and Knowles are the adders discussed in this research. Further, the combinations of any two adders have also been tested for the best efficiency in terms of power consumption and delay utilisation. From the many combinations, it is found that the proposed combination of Bruntkung and SKlansky (BSK) adder performs excellent with the power consumption of 25011.22 nW and delay of 1243 pS.