Open AccessImplementation of Low Power Carry Skip Adder using Reversible Logic
Author(s) -
Addanki Purna Ramesh*
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.c5212.098319
Subject(s) - adder , toffoli gate , arithmetic , carry save adder , serial binary adder , transistor count , logic synthesis , computer science , logic gate , subtractor , pass transistor logic , power (physics) , mathematics , digital electronics , algorithm , electronic circuit , power consumption , electrical engineering , engineering , telecommunications , physics , quantum gate , quantum mechanics , quantum algorithm , quantum , latency (audio)
Addition is a vital arithmetic operation. It is the base of commonly used arithmetic operations such as division, subtraction, and multiplication. Adder is a digital circuit that accomplishes addition of numbers. The one bit full adder is the basic block of an arithmetic unit. There are several adder designs implemented so far to reduce the power. However, each design suffers from exact drawback. Reversible logic is the growing technology in the current era. The numbers of input and output lines in reversible logic are equal. In reversible logic the inputs are to be recovered from the outputs. Reversible logic gates are defined by the user. In this paper Carry Skip Adder (CSKA) is implemented in two different designs i.e. design-I and design-II. Design-I is implemented using Peres gates with irreversible (XOR, AND, OR) logic gates. Design-II is implemented using PERES, TOFFOLI, and FREDKIN reversible logic gates. Design-I and design-II designs are synthesized and simulated by Mentor Graphics tool. Design-II is more efficient in terms of transistor count and power consumption compared to DesignI.