Open AccessA Secure Architecture of Design for Testability Structures
Author(s) -
K. Swaraja,
K. Meenakshi,
Padmavathi Kora,
Mamatha Samson,
G. Karuna,
A. Ushasree
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b18840.078219
Subject(s) - testability , test vector , key (lock) , overhead (engineering) , computer science , design for testing , linear feedback shift register , polynomial , built in self test , dimension (graph theory) , fault coverage , computer engineering , embedded system , theoretical computer science , shift register , mathematics , chip , test set , reliability engineering , engineering , computer security , artificial intelligence , telecommunications , programming language , mathematical analysis , electronic circuit , electrical engineering , pure mathematics