Open AccessDesign and Implementation of Rearrangable Non-Blocking Switching Network in VLSI
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b1356.0982s1119
Subject(s) - clos network , multistage interconnection networks , computer science , latency (audio) , interconnection , computer network , blocking (statistics) , lan switching , key (lock) , network switch , class (philosophy) , telecommunications , operating system , burst switching , transmission delay , artificial intelligence , network packet
The main goal of this article is to implement an effective Non-Blocking Benes switching Network. Benes Switching Network is designed with the uncomplicated switch modules & it’s have so many advantages, small latency, less traffic and it’s required number of switch modules. Clos and Benes networks are play a key role in the class of multistage interconnection network because of their extensibility and mortality. Benes network provides a low latency when compare with the other networks. 8x8 Benes non blocking switching network is designed and synthesized with the using of Xilinx tool 12.1.