Open AccessFPGA Implementation of Fault Tolerant Full Adder Design for High Speed VLSI Architectures
Author(s) -
Vikas Maheshwari,
R. B. Singh
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b1248.0782s319
Subject(s) - adder , field programmable gate array , disappointment , computer science , block (permutation group theory) , very large scale integration , computer architecture , chip , parallel computing , arithmetic , fault tolerance , spartan , embedded system , computer hardware , mathematics , psychology , distributed computing , telecommunications , social psychology , geometry , latency (audio)
The essential goal is to distinguish and diminish the deficiencies in full Adder configuration making use of Self checking and Self Repairing Adder Block. The tempo of chip disappointment is straightforwardly relative to chip thickness. A framework should be flaw tolerant to diminish the frustration rate. The nearness of different troubles can demolish the usefulness of complete snake. This paper displays a region proficient flaw tolerant complete snake shape that may repair issues without interfering with the everyday assignment of a framework. The combo and duplicate is finished through way of making use of Xilinx ISE 14.7 and actualized on FPGA Spartan three..