Open AccessFIR Filter Design using Floating Point Column Bypassing Technique
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b1079.0782s419
Subject(s) - multiplier (economics) , rounding , finite impulse response , computer science , filter design , booth's multiplication algorithm , filter (signal processing) , digital signal processing , digital filter , software , computer hardware , adder , electronic engineering , algorithm , engineering , telecommunications , latency (audio) , economics , computer vision , macroeconomics , programming language , operating system
This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.