Open AccessDesign of a High Speed and Area Efficient Novel Adder for AES Applications
Author(s) -
A. Radha,
K.S.N. Murthy
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b1057.078219
Subject(s) - adder , computer science , carry save adder , serial binary adder , arithmetic , computer hardware , very large scale integration , electronic circuit , digital signal processing , parallel computing , embedded system , electrical engineering , engineering , mathematics , telecommunications , latency (audio)
In the design of VLSI circuits, there is huge power consumption because of circuit complexity. It is known that the demand for portable equipment is rapidly increasing now a days. Recently power efficient circuit designs have been concentrated. In complex arithmetic circuits adder is the most important building block. These are widely used in some other applications also like Central Processing Units, Arithmetic Logic Units and floating-point units. In case of cache memory access and in digital signal processing, these are used for address generation. Adders are most significant in control systems also. The speed of a processor and system accuracy is based on the performance of this adder. Regularly, Ripple Carry Adder is elected for two N-bit numbers adder due to fast design time of these RCAs among various other types of adders. Even though if RCA has fast design time, but it is limited in time because of that each full adder must wait for the carry bits of previous full adder blocks. A carry tree adder is proposed in this paper which is efficiently implemented technique at gate level for decreasing the delay and decreasing the memory usage.