Open AccessA Metaheuristic Algorithm for VLSI Floorplanning Problem
Author(s) -
Sitalakshmi Venkatraman,
M. Sundhararajan
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b1052.0782s519
Subject(s) - floorplan , very large scale integration , harmony search , benchmark (surveying) , computer science , algorithm , genetic algorithm , chip , parallel computing , mathematical optimization , mathematics , embedded system , artificial intelligence , telecommunications , geodesy , geography
Floorplanning plays an important role within the physical design method of very large Scale Integrated (VLSI) chips. It’s a necessary design step to estimate the chip area before the optimized placement of digital blocks and their interconnections. Since VLSI floorplanning is an NP-hard problem, several improvement techniques were adopted to find optimal solution. In this paper, a hybrid algorithm which is genetic algorithm combined with music-inspired Harmony Search (HS) algorithm is employed for the fixed die outline constrained floorplanning, with the ultimate aim of reducing the full chip area. Initially, B*-tree is employed to come up with the first floorplan for the given rectangular hard modules and so Harmony Search algorithm is applied in any stages in genetic algorithm to get an optimum solution for the economical floorplan. The experimental results of the HGA algorithm are obtained for the MCNC benchmark circuits