Open AccessHigh-Throughput Low-Area Hardware Design of Authenticated Encryption with Associated Data Cryptosystem that Uses ChaCha20 and Poly1305
Author(s) -
Guard Kanda,
Kwangki Ryoo
Publication year - 2019
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.b1017.0782s619
Subject(s) - computer science , modelsim , advanced encryption standard , verilog , hardware architecture , encryption , embedded system , throughput , computer hardware , stream cipher , cryptography , correctness , aes implementations , field programmable gate array , software , vhdl , algorithm , computer network , operating system , wireless
In this paper, the hardware design of a low area and a high throughput ChaCha20-Poly1305 that performs the dual authentication-encryption function for a secured communication within hardware devices is presented. Cryptographic algorithms- ChaCha20 stream cipher and Poly1305, enhance security margins and achieve higher performance measures on a wide range of software platforms and has proven superior to its counterpart, the AES, in the software domain. This relatively new stream cipher is compared to the benchmark AES, has recently been standardized but their implementations in hardware have had very little to not very desirable results particularly in terms of area. For this reason, it is therefore an active field to make such algorithms hardware friendly. This research presents a compact, low-area and high throughput chacha20-Poly1305 Authenticated Encryption with Associated Data (AEAD) design. The core architecture consists of the ChaCha20-Poly1305 algorithm. The simplified quarter round designed in the proposed architecture uses the addition, rotation and exclusive-or algorithms operators (gates). This proposed architecture provides an improvement in the operating frequency and area. The architecture was modeled and simulated with Verilog HDL and Modelsim tools for functional and timing correctness. The hardware architecture designed was synthesized with Xilinx‟s Synthesis Tool (XST) and Synopsis‟ Design Compiler (DC) using the 0.18µm CMOS standard Cell library. The resulting hardware area in terms of gate equivalent is approximately 11KGE for chacha20 and 21KGE for Poly1305. The design operates at maximum frequency of 420 MHz and 870 MHz for the ChaCha20 and Poly1305 respectively. The proposed design presented in this paper additionally functions at a throughput of approximately 8 Gbps for ChaCha20 with an overall efficiency of 2.35 Kbps/GE when ChaCha20 and Poly1305 are combined into the AEAD_ChaCha20_Poly1305 authenticated encryption core.