Open AccessReduction of Power in General Purpose Processor Through Clock-Gating Technique
Author(s) -
R. Rao,
P. Bala Murali Krishna,
Sachit Chandra,
Shaik Fairooz,
P. Prasanna Murali
Publication year - 2021
Publication title -
international journal of recent technology and engineering
Language(s) - English
Resource type - Journals
ISSN - 2277-3878
DOI - 10.35940/ijrte.a5927.0510121
Subject(s) - clock gating , computer science , microprocessor , digital clock manager , clock skew , computer hardware , cpu multiplier , clock domain crossing , block (permutation group theory) , embedded system , electrical engineering , clock signal , power (physics) , synchronous circuit , electronic engineering , electronic circuit , engineering , physics , geometry , mathematics , quantum mechanics
Now a days DC power supply plays very importantrole in the Electronic industry because for every electronic gadgetDC power is required to operate it. Even though durable DCbatteries are available in the market to operate the variouselectronic gadgets for more time, electronic designers arecontinuously concentrating more and more to reduce the powerthrough the various new Technologies like increasing paralleloperations, pipe line concepts [1] etc. To work such durablebatteries more duration than the actual duration what they cangive, in this work we are concentrating on the 'clock-gating'technique to reduce the power in the general purposemicroprocessor. For every microprocessor clock is required. Alloperations of any processor are performed by the clock cycle.There are various blocks in the processor but all the blocks are notoperated at a time while using it, some blocks in the off modewhile other blocks are in the working mode. Hence in order topower off such blocks for a little while clock gating is used in thiswork. Wherever particular block is not operated, for that blockclock is disabled by the clock gating technique. The main principleof clock getting is nothing but ANDing the processor clock with agate-control signal.