Design and Simulation of Low Power Consuming Digital Controlled Oscillator in All Digital Phase Locked Loop

Recent IC technology innovations can achieve lowpowe r biomedical implant functionality.RF transceivers require low-power and small-sized components in biomedical implants to achieve the best results in frequency and phase control. Phase Locked Loop (PLL) is the key component for controlling these parameters in low power consumption RF transceivers. Therefore All Digital Phase Locked Loop (ADPLL) is chipping effectively into a major role in the fields of Biomedical & Communication. ADPLLs contribute better results in these areas due to their efficient blocks. This paper focuses on the design of low-power Digital Controlled Oscillator (DCO) and provides information on the various ADPLL blocks. To reduce power dissipation DCO is designed with XNOR gate using delay elements by avoiding direct contact between VDD & GND and the MOS transistors were arranged in ring topology. Tanner tools were used to design and simulation. In addition to this it also provides the detailed history of PLLs & ADPLLs and their mathematical analysis. Compared to previous design, the current DCO design gives better power consumption results.