Open AccessSEU Performance Enhancement in BPJLT Devices by Channel Doping and Film Thickness
Author(s) -
N. Vinodhkumar,
C. Raja,
Satish Addanki
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.l2865.1081219
Subject(s) - doping , materials science , cmos , optoelectronics , planar , scalability , channel (broadcasting) , transistor , silicon , performance enhancement , electronic engineering , engineering physics , electrical engineering , computer science , engineering , voltage , medicine , computer graphics (images) , database , physical medicine and rehabilitation
The bulk planar junctionless transistor (BPJLT) is a potential candidate for future CMOS technologies due to its CMOS compatibility and scalability. In this paper, the impact of silicon film thickness and channel doping on single-event upset (SEU) radiation performance of BPJLT based SRAMs is studied using TCAD simulations. The simulation results show that BPJLT devices having higher channel doping and smaller film thickness provides the better SEU performance.