Open AccessDesign of Low Power Transceiver on Spartan-3 and Spartan-6 FPGA
Author(s) -
Keshav Kumar,
Amit Kant Pandit,
Shri Mata,
Vaishno Devi,
Yousef Baker El-Ebiary,
Salameh Mjlae
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.l1006.10812s19
Subject(s) - universal asynchronous receiver/transmitter , spartan , field programmable gate array , transceiver , power (physics) , computer science , transmitter , embedded system , electrical engineering , computer hardware , engineering , chip , cmos , physics , channel (broadcasting) , quantum mechanics
In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.