Open AccessA Low Power, High Speed 18-Transitor True Single-Phase Clocking D Flip- Flop Design In 90nm Cmos Technology
Author(s) -
Shanti Kasani,
G. R. L. V. N. Srinivasa Raju
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.k2531.0981119
Subject(s) - cmos , flip flop , transistor , pass transistor logic , computer science , electronic engineering , logic gate , transistor count , electrical engineering , engineering , voltage
In this paper the authors came up with a contemporary low power, high-speed 18- transistor true singlephase clocking D flip-flop (FF) design using complementary pass-transistor logic. This design is a master-slave-type logic structure and hybrid logic design consisting of complementary pass-transistor logic style and static CMOS logic style. In order to reduce the number of transistors and to simplify the circuit complexity complementary pass-transistor logic style is used. In this design state transition is faster in the slave latch which enhances time performance using a virtual VDD technique. The circuit is designed using GPDK 90nm CMOS technology and the simulation results show better performance indices such as average power consumption, clock- to-Q delay, data-to-Q delay, PDP and area of utilization.