Open AccessAn Innovative Low Power Reversible ALU for Quantum Processor using QCA
Author(s) -
Rajinder Tiwari,
Vikas Rajiv,
Preeta Sharan,
Anil Kumar
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.k1738.1081219
Subject(s) - verilog , computer science , dissipation , power (physics) , computation , reversible computing , logic gate , cadence , adder , parallel computing , quantum computer , field programmable gate array , electronic engineering , embedded system , quantum , algorithm , engineering , telecommunications , physics , quantum mechanics , thermodynamics , latency (audio)
Landauer stated that “For irreversible computation each loss in information leads to loss of kTln2 joules of heat energy”. This has led to considerable interest in reversible logic. We know that ALU is the most basic part in any processor. Processor quality is determined based on its speed of operation. But, as the size of a processor decreases we face problems like power dissipation and greater delays. So, this paper presents an ALU implemented using reversible logic. This design is a simple way to reduce power dissipation and delay to a certain extent. Verilog HDL programming has been used to make this design. We have used XILINX and CADENCE tool to simulate this model and obtain power and delay analysis.