Open AccessDesign a High Speed Multiplier using Two Phase PPA
Author(s) -
Gajula Lakshminarayana,
Shri Scholar,
Gurunadha Moparthy,
Meduri Anupama,
Amol Deshpande
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.k1023.09811s219
Subject(s) - adder , multiplier (economics) , prefix , arithmetic , ripple , computer science , carry save adder , carry (investment) , reduction (mathematics) , electronic engineering , mathematics , algorithm , electrical engineering , engineering , telecommunications , voltage , linguistics , philosophy , geometry , finance , economics , macroeconomics , latency (audio)
Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.