Open AccessImplementation of Phase Frequency Detector in Phase locked loop using Preset able modified TSPC D flip-flop
Author(s) -
Mrs.S. Praseetha*,
Ms.Benedict Tephila M,
Ms.Anusuya S
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.j9828.1081219
Subject(s) - phase locked loop , pll multibit , pmos logic , flip flop , phase frequency detector , frequency multiplier , multiplier (economics) , phase detector , power consumption , electronic engineering , power (physics) , electronic circuit , loop (graph theory) , computer science , electrical engineering , voltage , engineering , transistor , physics , phase noise , cmos , charge pump , mathematics , capacitor , quantum mechanics , combinatorics , economics , macroeconomics
Phase locked loop (PLL) forms an important part in many applications. Here design of PLL for frequency multiplier operation is considered. Frequency multiplier operation is implemented by using Preset able Modified Single Phase Clock (MTSPC) D flipflop logic circuits in Phase Frequency Detector (PFD). Preset able Modified Single Phase Clock (MTSPC) D flipflops functions at high speed with less power consumption. Noises in the form of glitches are introduced when a preset-able true single phase clocked D flipflop (TSPC) used in Phase Locked Loop. Preset-able modified TSPC (MTSPC) D flipflop used to overcome these glitches caused due to toggling at the output by use of PMOS. Technology applied is 90nm technology. Applications where better speed and reduced power consumption are required, this type of Phase locked loop (PLL) can be utilized.