Open AccessLow Power High Throughput Memory Less Adaptive Filter using Distributed Arithmetic
Author(s) -
Paida Chiranjeevi,
B. Venkatesh
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.j9219.0881019
Subject(s) - throughput , computer science , adder , multiplexer , lookup table , filter (signal processing) , computer hardware , filter design , finite impulse response , block (permutation group theory) , parallel computing , algorithm , multiplexing , mathematics , telecommunications , geometry , wireless , computer vision , programming language , latency (audio)
This paper briefs an area efficient, low power and high throughput LMS adaptive filter using Distributed Arithmetic architecture. The throughput is increased because of parallel updating of filter coefficient and computing the inner product simultaneously. Here we have proposed memory-less design of distributed arithmetic (MLDA) unit. The proposed design uses 2:1 multiplexer’s architecture to replace LUT of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed architecture requires more than half area that required for the existing LUT based inner product block. The proposed design is implemented in synopsis design compiler and the result shows that the area decreased by 52.7% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap N=16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP).