Open AccessDesign of Fast Efficient Radix-16 Sequential Multiplier
Author(s) -
B. Gokul,
M. Padmaja
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.j9180.0881019
Subject(s) - adder , radix (gastropod) , arithmetic , multiplier (economics) , carry save adder , power–delay product , cadence , computer science , booth's multiplication algorithm , multiplication (music) , computer hardware , mathematics , parallel computing , electronic engineering , engineering , telecommunications , latency (audio) , botany , macroeconomics , combinatorics , economics , biology
Multiplication is an important function in computer arithmetic operations. The multiplication process will be done by the shift-and-add sequential multiplication procedure. Radix-16 sequential multiplier design generates the radix-16 partial products as two low (L) and high (H) components. In order to reduce cycle time, Brent-Kung adder and two radix 16 carry-save adders are used to generate radix-16 partial products. The proposed design of radix-16 sequential multiplier is efficient over previous designs and comparison depicts ADP and PDP of existing method are 11.22% and 8.45% than proposed method. However, the Excess area-Delay product and Excess-power-Delay product is also lowered. The design is carried out in Xilinx ISE 14.5 software and cadence tool for simulation and synthesis results. Fast efficient radix-16 sequential multiplier can be used in many digital signal processing applications