Open AccessLong Channel Keeper based Open Loop Difference Amplifier Domino for Noise Tolerant Low Power OR Gates
Author(s) -
Manish Tiwari*,
Vijayshri Chaurasia
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.j1221.0881019
Subject(s) - domino logic , domino , electronic engineering , cmos , computer science , logic gate , pass transistor logic , amplifier , electrical engineering , engineering , transistor , voltage , biochemistry , chemistry , catalysis
This paper proposes an open loop difference amplifier with long channel keeper technique for domino logic circuits implemented as wide fan in OR gate. Currently OR gates suffer from high capacitive loading and delays due to such loading. The proposed design uses single stage of comparison and dual keeper arrangement to generate and hold the output logic state. This technique effectively reduces the high input loading from capacitance and manages the power consumption by switching based on the generated difference voltage. As compared to standard footerless domino SFLD, the proposed design OLDA has shown to reduce power consumption by 42% in 64 bit configuration. It has increased average noise immunity by 2.03 times, while maintaining same speed as compared to SFLD. All simulations are done in CMOS technology with 90nm PTM LP models