Open AccessDesign of A Fault Tolerant Razor Flip Flop Sklansky Adder for Delay Reduction in FIR Filter
Author(s) -
A.V.S.S. Varma,
Kasiprasad Mannapalli
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i8986.078919
Subject(s) - adder , fault tolerance , computer science , flip flop , reduction (mathematics) , filter (signal processing) , finite impulse response , reliability (semiconductor) , computer hardware , algorithm , mathematics , telecommunications , distributed computing , enhanced data rates for gsm evolution , geometry , computer vision , latency (audio) , power (physics) , physics , quantum mechanics
Basically, to reduce the failure rate in the system, we need to introduce the fault tolerant system. Because of multiple faults occurred in the system, the system will increase the area. To employ the adder architecture, different algorithms are used in digital signal processing. By introducing the fault tolerant system, the reliability of the proposed system will increase. So in this paper we introduced the design of fault tolerant razor flip flop using SKLANSKY adder for delay reduction in FIR filter. The razor flip flop will increase the energy efficiency of proposed system. This flip flop will store the information by latching the circuit. The SKLANSKY adder is the part of arithmetic logic unit. In proposed system, all bits are summed and followed to the fault tolerance system,. This fault tolerance system will detect the error and give efficient output. Hence compared to existed system, the proposed system gives high performance and accuracy in terms of delay.