Open AccessFFT using Power Efficient Vedic Multiplier
Author(s) -
Nidhi Gaur,
Anu Mehra,
Pradeep Kumar
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i8922.0881019
Subject(s) - fast fourier transform , adder , multiplier (economics) , digital signal processing , field programmable gate array , computer science , arithmetic , multiplexer , parallel computing , computer hardware , very large scale integration , computer architecture , embedded system , mathematics , multiplexing , algorithm , telecommunications , economics , macroeconomics , latency (audio)
Modern communication systems rely on Digital Signal Processing (DSP) more than ever before. Improving the speed of FFT computation using high speed multipliers will help to enhance the performance of DSP systems. In this paper a DIT FFT architecture using high performance Modified Vedic multipliers is proposed. Vedic Multipliers offer a more efficient way to perform multiplication on large numbers occupying less area and consuming low power and delay The adders used in the Vedic multipliers are Brent Kung based and multiplexer based adders. The right utilization of these adders at different word lengths helps to achieve an architecture with minimal area and power. Comparative analysis of modified 24×24 Vedic Multiplier with existing Vedic Multiplier shows the improvement in performance with respect to power and area. Proposed FFT design is compared with existing designs for dynamic power consumption and an improvement of 46.93% compared to Tsai’s FFT Design and 59.37% compared to Coelho’s FFT Design is achieved. The entire architecture is implemented on Virtex 7 FPGA and simulated using Xilinx Vivado 2017.4.