Open AccessDesign and Implementation of Compressor based 32-bit Multipliers for MAC Architecture
Author(s) -
M. Abheesh Kumar,
Anil Kumar Sudhakar,
Jami Venkata Suman
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i8517.078919
Subject(s) - multiplier (economics) , adder , computer science , application specific integrated circuit , field programmable gate array , computer hardware , gas compressor , cmos , digital signal processing , 16 bit , arithmetic , microprocessor , embedded system , electronic engineering , latency (audio) , computer architecture , mathematics , engineering , mechanical engineering , telecommunications , economics , macroeconomics
Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.