Open AccessDesign and Implementation of RNS Filter using Modular-Multipliers
Author(s) -
P. Bhargavi,
K. Srinivasa Reddy,
M. Durga Prakash
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i8117.078919
Subject(s) - adder , computer science , pmac , finite impulse response , computer hardware , verilog , electronic engineering , computer architecture , embedded system , field programmable gate array , latency (audio) , algorithm , engineering , electrical engineering , telecommunications , control system
In this paper, an efficient RNS based multiply-accumulate (MAC) unit is proposed to implement residue number system (RNS) based finite impulse response filter (FIR). The proposed MAC (PMAC) approach reduces the number of adders in critical path delay. In this work, a FIR filter with PMAC approach is implemented using structural Verilog HDL language. The United Microelectronics Corporation 90 nm technology library has been used for synthesis. The performance metrics such as area, power and delay are obtained using Cadence RTL compiler. The synthesis results shows that RNS filter with PMAC improves clock frequency and reduces delay and area when compared to conventional MAC (CMAC).To compare the performance of the filters power delay product (PDP) is also considered. The PMAC architecture has improved PDP gain by 30.63% when compared to CMAC.