Open AccessDelay Approximation Model for Prime Speed Interconnects in Current Mode
Author(s) -
R. Naraiah,
B. Balaji,
E. Radhamma,
Rajender Udutha
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i8019.078919
Subject(s) - interconnection , capacitance , very large scale integration , inductance , chip , prime (order theory) , electronic engineering , computer science , coupling (piping) , electrical engineering , topology (electrical circuits) , physics , engineering , voltage , mathematics , telecommunications , mechanical engineering , electrode , quantum mechanics , combinatorics
There is enormous demand for high speed VLSI networks in present days. The coupling capacitance and interconnect delay play a major role in judging the behavior of on chip interconnects. There is an on chip inductance effect as we switch to low technology that leads to delay in interconnecting. In this paper we are attempting to apply second order transfer function designed with finite difference equation and transform Laplace at the ends of the source and load termination. Analysis shows that the current signaling mode in VLSI interconnects provide better time delay than the voltage mode