Open AccessInterrupt Enabled Priority Based Master Slave Communication using SPI Protocol
Author(s) -
Deepika,
Jayanthi K Murthy
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i7649.079920
Subject(s) - interrupt , computer science , interface (matter) , embedded system , microcontroller , block (permutation group theory) , protocol (science) , synchronous serial communication , serial communication , transfer (computing) , computer hardware , master/slave , communications protocol , operating system , serial port , medicine , geometry , mathematics , alternative medicine , bubble , pathology , maximum bubble pressure method
Serial Peripheral Interface or SPI is a synchronous serial communication protocol that provides full – duplex communication at very high speeds. It is a master – slave type protocol that provides a simple and low-cost interface between a microcontroller and its peripherals. This paper proposes the design of a priority-based master slave communication system using SPI Protocol that enables the system to operate using interrupts. The design mainly emphasizes on priority-based communication where the slaves will generate an interrupt over a newly defined interrupt pin when some data transfer needs to happen. When the master receives an interrupt from the slave it establishes communication with one slave at a time based on the priority and the priority to each slave is assigned by the arbiter or priority control block. The highest priority slave is served first. Shift register is used to store and transfer the data bit by bit and it resets every time a data transfer is complete. The design proposed here can be implemented in different applications which involve the peripherals that can support SPI protocol for communication such as LCDs, Analog to Digital Converter, Digital to Analog Converter, Memory Cards, Temperature Sensor, Pressure Sensor. In this work, a single master multi slave architecture is considered. The design given in this paper can be scaled up to support more than four slaves.