Open AccessA Layout Technique to Reduce the Impact of Parasitic Capacitors Within A Capacitor Array on the Nonlinearity of Data Converters
Author(s) -
Santosh Kodekal,
Prof. Raji. C*.
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i7634.078919
Subject(s) - capacitor , converters , resistor , parasitic extraction , differential nonlinearity , electronic engineering , integral nonlinearity , nonlinear system , data conversion , linearity , computer science , successive approximation adc , matching (statistics) , electrical engineering , engineering , voltage , cmos , computer hardware , physics , mathematics , statistics , quantum mechanics
SAR ADC has a moderate speed, Low area and low cost compared to other ADC implementations. The accuracy expected from a commercial SAR ADC is very high and research has been going on for many years to improve the accuracy. The Linearity of the data converters is the key for accuracy. The Integral nonlinearity and differential nonlinearity errors of data converters are governed by the matching of the unit capacitors/resistors with in capacitor/resistor array. Layout of these arrays can add significant parasitics affecting the nonlinearity of data converters. This paper presents a layout technique to reduce the impact of the parastics on data converter’s nonlinearity.