Open AccessAccounting for PVT Variations in Design Timing Closure
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.i3042.0789s319
Subject(s) - chip , closure (psychology) , computer science , process variation , variation (astronomy) , process (computing) , power (physics) , accounting , reliability engineering , engineering , telecommunications , business , economics , physics , quantum mechanics , astrophysics , market economy , operating system
The On Chip Variation (OCV) refers to changes in the behavior of parameters like process, voltage and temperatures on a chip. In this paper, we go through different approaches followed to compensate for PVT variations on chip during design timing closure. We review the dominant approaches used for accounting such variations. We also review the advantages and disadvantages of these approaches used based on the ease of use, implementation, power, area, and the overheads involved in adopting them.