Open AccessEnhanced Scan Segmentation for Low Power DFT
Author(s) -
Shalini Pathak,
Anuj Grover,
Mausumi Pohit
Publication year - 2019
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.h7428.078919
Subject(s) - segmentation , scan chain , image stitching , computer science , cmos , artificial intelligence , power (physics) , electronic engineering , integrated circuit , engineering , physics , quantum mechanics , operating system
Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT). We propose an enhanced scan segmentation method using logic cluster controllability (LoCCo) technique for scan chain stitching to reduce test power efficiently. After LoCCo based scan stitching, since the trailing edge of scan chains contain very less switching transitions, we optimize the number of segments needed. This enables segmentation hardware reduction and still achieve lower power scan test compared to conventional method. Test cases prepared from ITC’99 standard circuits and industrial designs in 40nm CMOS and 28FDSOI technology were used for comparison. LoCCo based scan segmentation gave a shift power reduction of up-to 21.7% over conventional scan segmentation. Up-to 8.6%, shift power gain was observed even with 25% reduced segmentation when enhanced scan segmentation technique is used