Open Access64bit Hybrid Adder for ALU Design Applications
Author(s) -
Hema Singaravelan*,
S. Ravi
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.h6646.069820
Subject(s) - adder , modelsim , carry save adder , serial binary adder , carry (investment) , computer science , verilog , arithmetic , schematic , computer hardware , parallel computing , field programmable gate array , mathematics , vhdl , electronic engineering , engineering , telecommunications , finance , economics , latency (audio)
The Arithmetic Logic Unit is an important component of any Central Processing Unit. An improvement of the speed, area, and power consumption of an ALU directly promotes the performance of the system. Thus, optimization of the ALU design is necessary and for this reason several common adders such as the ripple carry adder, etc. and a proposed model of a 64bit hybrid adder were designed, and a comparative analysis of their performance was studied. The proposed hybrid adder was developed using an 8bit Ripple Carry adder that evaluates the LSB followed by a Carry skip adder block consisting of a 4bit Carry Skip Adder, an 8bit Carry Skip, another 8bit Carry Skip, followed by a 4bit Carry Skip Adder, and finally the MSB is calculated by a 32bit Carry Select Adder. The adders were designed in Verilog on ModelSim-Altera 10.1d (Quartus II 13.0sp1) and later the schematic was obtained on Genus Synthesis (RTL Compiler) of Cadence for ASIC design using 45nm technology. Each adder showed some advantages, but the proposed hybrid adder optimized all aspects of the model while increasing the speed of the device.