Open AccessAnalysis of Low Power Dynamic Comparator
Author(s) -
M. Sai Navya*,
Umamaheswara Reddy,
Nishant Kumar,
G. Sai Krishna,
Lakshman Pappula
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.g5294.059720
Subject(s) - comparator , dissipation , converters , electronic engineering , power (physics) , electronic circuit , computer science , dynamic demand , sizing , transistor , electrical engineering , voltage , engineering , physics , art , quantum mechanics , visual arts , thermodynamics
Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%.