Open AccessTSV Optimized Test Wrapper Design for Fine Grain Partitioned 3D System on Chip
Author(s) -
Harpreet Vohra,
Ashima Singh
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.g4957.059720
Subject(s) - benchmark (surveying) , interconnectivity , three dimensional integrated circuit , reduction (mathematics) , chip , embedded system , system on a chip , heuristic , computer science , through silicon via , electronic engineering , engineering , electrical engineering , geometry , mathematics , geodesy , artificial intelligence , wafer , geography , telecommunications
The 3D System-on-chip (SoC) technology supports the vertical interconnectivity required for the purpose of functional, supply and test access purposes through the use of Through Silicon Vias (TSVs). Little number of available TSVs for test purpose necessitates the optimization of test infrastructure. This paper proposes an algorithm to design the test wrapper for the 3D cores such that the number of the TSVs used per TAM chain are minimized. Test time optimization is done by balancing the lengths of the individual Wrapper chain inside the core. The proposed heuristic firstly distributes the different core elements on the given TAM chains and then uses a diagraph for their insertion ordering to get minimum possible TSV utilization. Simulation results are presented for the different cores of the ITC’02 SoC benchmark circuits. Results show that TSVs can be reduced to 20-30 percent with around 60-70 percent reduction in CPU time utilization for heavy SoCs in comparison to the other proposed techniques.