Open AccessRealization of Various Topologies of Adders Based on H-Dycml
Author(s) -
Riya Jain,
Neeta Pandey
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.f4592.049620
Subject(s) - adder , computer science , electronic engineering , cmos , power–delay product , power (physics) , realization (probability) , dissipation , network topology , engineering , mathematics , statistics , physics , quantum mechanics , operating system , thermodynamics
Power consumption minimization in a circuit becomes imperative with growth in demands of portable goods. However, at the same time, its speed limits the performance of a system. Therefore, there is a need of choosing optimum circuit architecture that takes into account the both conflicting parameters, that is, power dissipation and speed. Arithmetic unit is one of the vital components of portable goods and out of all arithmetic operations, adders are the most commonly used. To address the issue of high power dissipation, low-power designing styles are becoming prominent now-a-days. Hybrid Dynamic Current Mode Logic is high-speed, low-power designing style that has been recently proposed in literature. Therefore, this paper presents the comparison between performances of various topologies of adders that are implemented using a high-speed, low-power designing style: Hybrid-Dynamic Current Mode Logic (H-DyCML). All the circuits are realized in Cadence Virtuoso using 180nm CMOS technology parameter. Various performance parameters are evaluated such as: Delay, Power, Power-Delay Product, and hardware utilization. It is found that carry look-ahead adder out-stands other adders in terms of overall performance.