Open AccessDesign of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods
Author(s) -
C. Arunabala,
A. Lohithakshi,
D. Jyothsna,
CH. Pranathi,
A. Navaneetha
Publication year - 2022
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.e9850.0411522
Subject(s) - cmos , standby power , flip flop , voltage , transistor , electrical engineering , flops , computer science , leakage (economics) , leakage power , electronic circuit , backup , circuit design , cadence , electronic engineering , engineering , database , parallel computing , economics , macroeconomics
This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift registers, Analog and Digital circuit designs. And this circuit design is implemented in 45nm CMOS Technology Cadence Virtuoso Tool.