Open AccessDesign of a 4 bit Arithmetic and Logical unit with Low Power and High Speed
Author(s) -
C. Arunabala,
AUTHOR_ID
Publication year - 2021
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.e8660.0310521
Subject(s) - 4 bit , transistor count , adder , transistor , multiplexer , computer science , xor gate , arithmetic , computer hardware , arithmetic logic unit , 16 bit , logic gate , electronic engineering , electrical engineering , cmos , mathematics , engineering , algorithm , multiplexing , voltage , telecommunications
In this presented work we designed the 4- bit Arithmetic & Logical Unit (ALU) by using the different modules. The Various modules are AND gate & OR gate designed with six transistors, While the XOR modules is designed with both eight transistors & six transistors. The six transistor XOR module gives optimized results. Another one is the four by one multiplexer designed with eight transistors implemented using Pass transistor logic (PTL) style. The full adder module is designed by using 18 transistors implemented through PTL style. Here because of PTL style the number of transistor count optimized such that the constraints get optimized results. By using the AND, OR, XOR, 4X1 MUX and full adder modules with reduced transistor count we designed the one bit ALU. With one bit ALU we designed 4 bit ALU and compared the outcomes with conventional 4 bit ALU design so that the proposed 4 bit ALU design has optimized transistor count, area, power, delay and power delay product (PDP). Simulations are verified through 130nm mentor graphics tool.