Open AccessUrdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits
Author(s) -
M. Saranya,
M. Geetha Priya,
M Priyadharshini,
Ms. D. Vedhanivetha,
Mr. B. Lukman
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.e2130.039520
Subject(s) - arithmetic , multiplier (economics) , computer science , adder , multiplication (music) , dissipation , cadence , very large scale integration , spartan , parity bit , digital electronics , field programmable gate array , computation , electronic circuit , lookup table , logic gate , algorithm , mathematics , computer hardware , electronic engineering , embedded system , engineering , electrical engineering , telecommunications , programming language , physics , thermodynamics , combinatorics , economics , macroeconomics , latency (audio)
The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.