Open AccessNew Algorithm for Dht and Its Verilog Implementation
Author(s) -
Anamika Jain,
P. Pandey
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.d1910.029420
Subject(s) - very large scale integration , computer science , verilog , algorithm , simple (philosophy) , parallel computing , computation , discrete hartley transform , arithmetic , mathematics , field programmable gate array , computer hardware , embedded system , fourier analysis , mathematical analysis , philosophy , epistemology , fourier transform , fractional fourier transform
This paper presents a new algorithm for computing Discrete Hartley Transform (DHT) (type-2) of N with N=4r , where r>1.Paper also suggest VLSI architecture for the implementation of the newly developed algorithm. The computation of DHT using this algorithm is simple and requires less arithmetic operations compared with the general method for finding DHT. Also the suggested VLSI structure for the algorithm is regular and less complicated in terms of hardware requirement. Parallel processing of the algorithm make the processing further fast.