Open AccessFull Adder for Low Power Applications
Author(s) -
Mansi Jhamb,
Manoj Kumar,
. Vishal
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.d1846.029420
Subject(s) - adder , power–delay product , computer science , serial binary adder , electronic engineering , carry save adder , power (physics) , cmos , power analysis , electronic circuit , electrical engineering , computer hardware , engineering , cryptography , algorithm , physics , quantum mechanics
In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.