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Impact of Variation of Device Parameters on the Electrical Characteristics of Double-Gate Mosfets
Author(s) -
Shaik Jabeen,
Shrawan Kumar Jha,
P. Anuradha
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.c8640.019320
Subject(s) - transistor , mosfet , very large scale integration , materials science , field effect transistor , metal gate , cmos , nand gate , optoelectronics , threshold voltage , chip , gate oxide , electronic engineering , electrical engineering , computer science , logic gate , voltage , engineering
Very large scale integrated circuits (VLSI) have been possible owing to the shrinking of metal-oxide semiconductor field-effect transistors (MOSFETs). By reducing the dimensions of the device it is possible to have high density on the chip. This increases the number of logical functions that can be implemented on a given dimension of the chip. Along with the advantages associated with the shrinking of the devices, it also has certain drawbacks commonly known as short-channel effects. Due to these effects, device characteristics deviate from its expected values. There are many techniques through which these deviations can be minimized. One of the promising and highly researched techniques these days is the use of Multi-gate (MG) transistors in VLSI. Double-gate (DG) transistor is one among MG transistors. In DG MOSFET, substrate is surrounded by gates from two opposite sides. This leads to more control over the channel electrons by the gate terminals. In this paper, the consequence of change of various device constraints on the electrical characteristics of the DG MOSFETs will be investigated. Through the results, one can know to what extent the electrical properties changes when the dimensions and/or material properties are changed. This will be very helpful in determining the maximum current associated with those dimensions of DG MOSFETs.

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