Open AccessDesign of Completion Detectors in Asynchronous Communication System
Author(s) -
Norhuzaimin Julai*,
Shamsiah Suhaili,
Yonis M.Yonis Buswig
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.c8576.019320
Subject(s) - asynchronous communication , computer science , asynchronous system , asynchronous circuit , synchronizer , embedded system , verilog , synchronous serial communication , chip , computer hardware , synchronous circuit , computer architecture , clock signal , field programmable gate array , serial communication , distributed computing , computer network , telecommunications , jitter , serial port
In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.