Open AccessBuried Powered 4t Sram with Improved Write Margin
Author(s) -
Kamireddy Manohar,
M. Sri Hari,
MD. Basheer Ahamad,
Sai Krishna,
Lakshman Pappula
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.b7868.019320
Subject(s) - static random access memory , margin (machine learning) , computer science , electronic engineering , electrical engineering , engineering , computer hardware , machine learning
The main intention of this paper is to understand clearly about the high performance of 4T-SRAM with an improved write margin. the power consumption is often reduced considerably by using a buried power rail (BPR) to the SRAM cell, which reduces the resistance of bit line and word line. The write margin is often increased by the fine standardization of metal dimensions within the SRAM cell. Conventionally, 4T-SRAM cell offers high speed and fewer space compared to 6T-SRAM cell. 4T-SRAM is actualized using 130nm CMOS Technology.