Open Access891 Published By: Blue Eyes Intelligence Engineering & Sciences Publication (BEIESP) © Copyright: All rights reserved. Retrieval Number: B7821129219/2020©BEIESP DOI: 10.35940/ijitee.B7821.019320 Journal Website: www.ijitee.org Gain Error end DNL for Testing ADCs: Optimization in Time Domain
Author(s) -
Manish Jain,
Prof. R P Kumawat
Publication year - 2020
Publication title -
international journal of innovative technology and exploring engineering
Language(s) - English
Resource type - Journals
ISSN - 2278-3075
DOI - 10.35940/ijitee.b7821.019320
Subject(s) - effective number of bits , computer science , histogram , analog to digital converter , microcomputer , automatic gain control , electronic engineering , telecommunications , artificial intelligence , bandwidth (computing) , electrical engineering , engineering , chip , voltage , cmos , image (mathematics) , amplifier
Optimization in ADC is an important component which predicts overall accuracy of a system using it. Signals are in real time nature and it is necessary to convert these signals in digital form to interpret with digital form of signals and microcomputer based systems. ADC is used to carry out these conversions process from analog to digital. Determination of parameters of an ADC such as DNL, INL, SNR and ENOB are necessary for complete dynamic analysis and characterization of ADC. In frequently, application prerequisite input to an Analog to digital converter is time varying which requires determination of its parameters at corresponding frequency and different test conditions In order to test an ADC, it is necessary to first determine its code transition levels. Further Gain error, DNL are estimated using code transition level based on histogram technique. If there is an code transition level error introduced then effect of this error leads to error in estimate of gain, offset, DNL and ENOB. Further estimation of variance in different parameter values is analyzed in the proposed work.